The present invention relates to a method for fabricating a semiconductor device using a spacer patterning technology (SPT).
As the degree of integration of semiconductor devices has increased, the size and pitch of patterns that form circuits have been reduced. For forming a fine pattern in the semiconductor device, various manufacturing equipments and process methods have been suggested.
Photo lithography process (also called optical lithography) is a process used in micro fabrication to selectively remove parts of a thin film (or the bulk of a substrate). It uses light to transfer a geometric pattern from a photo mask to a light-sensitive chemical (photo-resist, or simply “resist”) on the substrate. According to Rayleigh's equation, the size of a fine pattern in a semiconductor device is in proportion to the wavelength of light used in the photo lithography process and is in inverse proportion to the size of the lens used in such a process. As a result, the wavelength of the lights used in the exposure process has been reduced or the size of lens has been increased in order to obtain a fine pattern. However, these methods require development of new manufacturing equipment and cause difficulty in management of the equipment; and, thus, manufacturing cost is increased.
For overcoming above described problem, there have been suggested other methods for forming a fine pattern of high integration by using conventional equipment, not new manufacturing equipment. One is a double patterning technology that performs an exposure process for patterning a photo-resist film with different masks twice to print a circuit pattern, and the other is a Spacer Patterning Technology (SPT) using a spacer as an etching mask for obtaining a fine pattern. Hereinafter, the SPT is described in detail.
FIGS. 1a to 1e are cross-sectional diagrams illustrating a SPT of a conventional semiconductor device, specifically, a method for forming a control gate of a flash memory device. Generally, the flash memory device includes a cell string connected to a plurality of (16 or 32) control gates and a switching transistor for connecting a Source Selection Line (SSL) and a Drain Selection Line (DSL) positioned at both ends of the cell string.
Referring to FIG. 1a, an etch target layer 110 is formed over a semiconductor substrate 100, and a sacrificial film 120 is formed over the etch target layer 110. The etch target layer 110 has a deposition structure including a polysilicon 110a and a nitride film 110b. The sacrificial film 120a includes a Tetra Ethyl Ortho Silicate (TEOS) oxide film. The deposition thickness of the sacrificial film 120a determines a height of a spacer used in the SPT.
A hard mask layer 160, a Bottom Anti-Reflection Coating (BARC) film 170 and a first photo-resist film are formed over the sacrificial film 120a. However, when an exposure process is performed, it is difficult to form a first fine photo-resist pattern defined in a mask by a difference in refractive indexes between a photo-resist film and the hard mask formed in the bottom of the photo-resist film. As a result, the BARC film 170 is used to prevent the photo-resist film 180 from being damaged by a light reflected due to a difference in refractive indexes between the photo-resist film and the hard mask.
Generally, an Anti-Reflection film has been used in a semiconductor lithography process as a thin light-absorbing photo-resist material layer used to form a fine circuit stably. In the Anti-Reflection film, a contact interface and a light characteristic are required to be well-fitting with a photo-resist material having high resolution used in a conventional process. The Anti-Reflection film regulates a substrate reflection index in a corresponding wavelength range to obtain a photo-resist pattern having no standing wave or no notching. Also, the Anti-Reflection film improves critical dimension (CD) uniformity and adhesiveness of the photo-resist pattern with the substrate. As a result, the Anti-Reflection film plays an important role in a DUV process. The Anti-Reflection film includes a top Anti-Reflection coating (TARC) film formed on the photo-resist film and a BARC film formed in the bottom of the photo-resist film. The BARC film has been widely used to obtain a fine circuit pattern.
Referring to FIG. 1a, the BARC film 170 and the hard mask layer 160 are etched with the first photo-resist pattern 180 as a mask. The sacrificial film 120a is etched with the patterned hard mask layer 160 to form a sacrificial pattern 120. After the sacrificial pattern 120 is formed, the first photo-resist pattern 180, the Anti-Reflection film 170 and the hard mask layer 160 are removed.
Referring to FIG. 1b, a spacer material layer is formed over the resulting structure including the sacrificial pattern 120. An etch-back process is performed to form a spacer 130 at sidewalls of the sacrificial pattern 120. The spacer 130 includes a polysilicon, and defines the control gate.
Referring to FIG. 1c, a wet etching process is performed to remove the sacrificial pattern 120 so that only the spacer 130 remains.
Referring to FIG. 1d, a second photo-resist pattern 140 for defining a gate of a switching transistor is formed in a peripheral region not in the middle region having a plurality of control gates formed in the semiconductor substrate 100.
The switching transistor connected to the SSL and DSL in the peripheral region is generally disposed at both ends of the cell string. In the exposure process, the switching transistor may have a defective focus rather than that of the control gates formed in the middle region. As defocus of the peripheral region becomes worse, a manufacturing margin of depth of focus (DOF) is insufficient. Also, the switching transistor for connecting the selecting lines SSL and DSL is related to turning-on of a channel so as to require accurate control on CD of positions and sizes of patterns. Furthermore, the sizes (widths) of the switching transistor and the selecting lines are larger than those of the control gates included in the cell string, so that it is difficult to form a fine pattern using the spacer 130. As a result, an additional second photo-resist pattern 140 is required in the peripheral region.
Referring to FIG. 1e, the etch target layer 110 is etched with the spacer 130 and the second photo-resist pattern 140 as a mask to form etch target patterns 155a and 155b that define a plurality of control gates and a gate of the switching transistor disposed at both ends of the cell string.
A third photo-resist pattern (not shown) is formed to expose the outer edge of the semiconductor substrate where the etch target patterns 155a and 155b are formed. The third photo-resist pattern (not shown) is a cutting mask for separating a spacer portion of a line end region generated in deposition of the spacer material layer. A part of the etch target patterns 155a and 155b disposed at the line end is removed with the third photo-resist pattern (not shown) as a mask to separate each line, and the third photo-resist pattern (not shown) is removed.
In the SPT, when the photo-resist pattern 140 having a pad type that defines a gate of the switching transistor is formed, a BARC film is formed before the photo-resist pattern 140 is formed, thereby preventing the photo-resist pattern 140 from being damaged. However, the BARC film cannot be formed due to the previously formed spacer 130. As shown in FIG. 1d, when the BARC film cannot be formed while the spacer 130 is formed, the photo-resist pattern 140 may have a defective profile and other defects.
Although the Anti-Reflection film may be deposited to have a given thickness in the peripheral region having no spacer 130 when the Anti-Reflection film is deposited while the spacer 130 is formed, the Anti-Reflection film is not formed in a fine region between the spacers 130 but deposited to have a high thickness. In this case, the Anti-Reflection film is deposited to improve profile and CD uniformity characteristics of the photo-resist pattern 140. However, when the etch target layer 110 is etched after the photo-resist pattern 140 having a pad type is formed, the method is required to include removing the Anti-Reflection film with the photo-resist pattern 140 as a mask. Also, the thickness of the photo-resist pattern 140 is required to increase, so that it is impossible to secure a process margin.
When the Anti-Reflection film is removed with an etching gas including CF4 as a base, the spacer 130 is attacked to decrease its height. As a result, an etching selectivity is insufficient in etching the etch target layer 110.
As mentioned above, in the conventional method for fabricating a semiconductor device, it is difficult to apply an Anti-Reflection film in formation of the photo-resist pattern 140 having a pad type, which results in notching due to reflection of lights, in defects of the photo-resist pattern formed in the peripheral region, in scum in a narrow region between patterns and in pattern lifting due to degradation of adhesiveness with the substrate.